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Schedule and Notes


Lecture
Schedule and Notes


Number
of Lectures
(90 minutes) 
Topic(s) 
Readings 
Lecture
Notes 
0.5 
 Course Syllabus and Policies
 Logic Design Overview 


1.5 
Digital Computers and Information:
 Âinary signals, information representation,
generic computer architecture
 Number systems, operations and conversions: decimal, binary, octal, hex.
 Codes: BCD, parity, Gray, ASCII, Unicode 


4 
Combinational Logic:
 Binary logic/gates
 Boolean Algebra, functions, properties and theorems
 Standard forms: minterms/maxterms, SoP, PoS
Karnaugh maps: 2, 3, and 4 variables maps
 QuineMcCluskey Boolean function minimization
 Twolevel/Multilevel circuit optimization



3 
Basic Logic Gates, popular technologies:
 NAND/NOR gates and circuits: twolevel and multilevel
implementations
 ExclusiveOR gates: odd function, parity function
 High impedance outputs: tristate buffers and transmission
gates
 Integrated circuits: levels of integration, digital logic
families, negative/positive logic
 CMOS circuits: switch models, nets of switches, fully
complementary CMOS, basic gates, complex gates, transmission
gate 


2 
Combinational Logic Design:
 Design principles (hierarchy, topdown design, CAD,
HDLs, logic synthesis)
 Combinational circuit analysis and timing
 Design procedure (examples)
 Technology mapping



6 
Combinational Functions and Circuits:
 Decoders, expansion, circuit implementation using decoders
 Encoders, expansion, priority encoders
 Multiplexers, implementation, QuadMUX, MUX as universal
gate
 Circuit implementation using MUXes
 Iterative Combinational Circuits
 Binary Adders (HA, FA, ripplecarry, carrylookahead)

Binary Subtraction (unsigned, 1's and 2's complements)
 Binary Adder/Subtractors
 Binary Adder/Subtractors (signed numbers)
 Binary Multiplication
 Other Arithmetic functions
 VHDL Language for Combinational Circuit Design
 Circuit implementation using PLDs (ROM, PLA, PAL) 


5 
Sequential Circuits:
 Latches (SR, S'R', D)
 Flipflops (MasterSlave, Edgetriggering)
 Characteristic Tables/Equations
 Asynchronous Set/Reset
 Sequential Circuit Analysis: Input Equations, State Tables,
State Diagrams
 Mealy Vs Moore machines
 Timing (FF and Circuit)
 Sequential Circuit Design: Design procedure, finding state
diagrams/tables, examples.
 Sequential Circuit Design: state assignment, designing
with D and JK flipflops, designing with unused states,
other design examples
 VHDL Language for Sequential Circuit Design 


1 
Registers:
 Registers with Load Enable and with Parallel Load
 Register Transfers
 Shift Registers, Shift Registers with Parallel Load, Bidirectional/Universal
Shift Registers
 Serial Transfer/Addition
 Shift Register in VHDL 


1 
Counters:
 Ripple Counters
 Synchronous Binary Counters: design with D and JK flipflops
 Serial and Parallel gating
 Binary UpDown Counter
 Binary Counter with Parallel Load
 BCD and Arbitrary Sequence Counters
 Modulo N counters
 Counters in VHDL 
Chapter 7 

Lecture notes provided here are indicative to the material
covered during this course. They DO NOT provide a detailed description
of the material covered in class.




