ECE 210: Digital Logic Design
Electrical and Computer Engineering,
University of Cyprus
Lecture Schedule and Notes

Number of Lectures
(90 minutes)
Lecture Notes
0.5 - Course Syllabus and Policies
- Logic Design Overview

Digital Computers and Information:
- Âinary signals, information representation, generic computer architecture
- Number systems, operations and conversions: decimal, binary, octal, hex.
- Codes: BCD, parity, Gray, ASCII, Unicode

pdf (bw)
4 Combinational Logic:
- Binary logic/gates
- Boolean Algebra, functions, properties and theorems
- Standard forms: minterms/maxterms, SoP, PoS
Karnaugh maps: 2, 3, and 4 variables maps
- Quine-McCluskey Boolean function minimization
- Two-level/Multilevel circuit optimization
Chapter 2,
Optimization Supplement,

Class Handouts
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3 Basic Logic Gates, popular technologies:
- NAND/NOR gates and circuits: two-level and multi-level implementations
- Exclusive-OR gates: odd function, parity function
- High impedance outputs: tri-state buffers and transmission gates
- Integrated circuits: levels of integration, digital logic families, negative/positive logic
- CMOS circuits: switch models, nets of switches, fully complementary CMOS, basic gates, complex gates, transmission gate

Chapter 2, 3.3, 6.1-6.2
CMOS Supplement& Notes

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2 Combinational Logic Design:
- Design principles (hierarchy, top-down design, CAD, HDLs, logic synthesis)
- Combinational circuit analysis and timing
- Design procedure (examples)
- Technology mapping
Chapter 3, 4.6,
Design Notes
pdf (bw)

Combinational Functions and Circuits:
- Decoders, expansion, circuit implementation using decoders
- Encoders, expansion, priority encoders
- Multiplexers, implementation, Quad-MUX, MUX as universal gate
- Circuit implementation using MUXes
- Iterative Combinational Circuits
- Binary Adders (HA, FA, ripple-carry, carry-lookahead)
- Binary Subtraction (unsigned, 1's and 2's complements)
- Binary Adder/Subtractors
- Binary Adder/Subtractors (signed numbers)
- Binary Multiplication
- Other Arithmetic functions
- VHDL Language for Combinational Circuit Design

- Circuit implementation using PLDs (ROM, PLA, PAL)

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Sequential Circuits:
- Latches (SR, S'R', D)
- Flip-flops (Master-Slave, Edge-triggering)
- Characteristic Tables/Equations
- Asynchronous Set/Reset
- Sequential Circuit Analysis: Input Equations, State Tables, State Diagrams
- Mealy Vs Moore machines
- Timing (FF and Circuit)
- Sequential Circuit Design: Design procedure, finding state diagrams/tables, examples.
- Sequential Circuit Design: state assignment, designing with D and JK flip-flops, designing with unused states, other design examples

- VHDL Language for Sequential Circuit Design

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- Registers with Load Enable and with Parallel Load
- Register Transfers
- Shift Registers, Shift Registers with Parallel Load, Bidirectional/Universal Shift Registers
- Serial Transfer/Addition
- Shift Register in VHDL

Chapter 7
VHDL Supplement

- Ripple Counters
- Synchronous Binary Counters: design with D and JK flip-flops
- Serial and Parallel gating
- Binary Up-Down Counter
- Binary Counter with Parallel Load
- BCD and Arbitrary Sequence Counters
- Modulo N counters
- Counters in VHDL

Chapter 7

Lecture notes provided here are indicative to the material covered during this course. They DO NOT provide a detailed description of the material covered in class.

  last updated : 09.09.2008