NEWS and UPDATES
Dec 23rd, 2008
Workshop Program
Schedule has now been announced.
WORKSHOP REGISTRATION
For each paper, at least
one author must register for and attend the workshop. Papers without
registered authors by the camera-ready deadline (December 23rd) will
NOT be included in the proceedings or the workshop program schedule.
Registration is available through the HiPEAC'09 Conference web site,
reachable via
http://www.hipeac.net/hipeac2009/index.php?form=form1.
Workshop authors
registered by December 18th will receive the early-bird registration
special.
TRAVELLING AND ACCOMMODATION
The HiPEAC'09 Conference website also
provides all necessary information for conference registration,
travelling and hotel accommodation and all other relevant
information.
http://www.hipeac.net/conference/index.php?page=home
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DEADLINE EXTENSION:
The deadline for submissions has been extended to November 20, 2008,
11:59PM PST.
PUBLICATION UPDATE
Selected papers will be
considered for inclusion on a special issue of the Transactions
on HiPEAC.
http://www.hipeac.net/journal
Motivation
To stimulate interest in an emerging and
challenging issue by bringing together researchers from various areas
(design, verification, test, architecture, fault tolerance and
reliability) to share ideas and ferment future research in holistic
approaches for reliable next-generation computing systems.
Reliable Systems Design
While technology is scaling well into the
nanometer era, design of reliable, dependable and verifiable systems
emerges as one of the most prominent design challenges. The increasing
rate of intermittent and permanent faults due to design errors, device
variability and manufacturing defects (including wear-outs),
environmental impact and aging of devices (degradation) rises
significantly as device size and power supply voltage shrink. Process
variation also shifts the traditional deterministic design methodology
towards a more stochastic and unorthodox design paradigm. The increased
design complexity, increased device parameter variations due to
manufacturing and lithographic defects, reduced noise margins resulting
from the power supply voltage reduction, and the increase of noise due
to crosstalk and power supply, all call for a design environment where
traditional design methodologies are no longer effective. These cause
further challenges in completing design verification and manufacturing
tests; such effects manifest as inherent unreliability of the
components, redefining the design and test paradigm for next-generation
computing systems. Additionally, energy reduction and performance
enhancement techniques force designs to run near zero margins, and
factors which cannot be controlled such as soft errors, thermal impact
and aging result in an increased occurrence of transient and hard faults
in computing systems.
Topics of interest include (but not limited to):
-
Dependable systems from
unreliable components, lifelong reliability
-
Fault-Tolerant
micro-architectures and system architectures
-
Testing and verification
strategies for the future
-
On-line (dynamic) testing and
verification techniques
-
Software-based methodologies for
fault tolerance and testing
-
System validation mechanisms
-
Built-in self diagnosis,
self-tuning and recovery schemes
-
Self-adaptive systems
-
System-level design and
integration for reliability, verifiability and dependability
-
Error modeling, detection,
correction, and tolerance for transient and permanent errors
-
Reliable on-chip communications
-
Energy/reliability/performance
tradeoffs
-
Aggressive power saving
mechanisms
-
Compiler/architecture/OS
methodologies and strategies for reliability
Workshop Organizers:
Alex Orailoglu (University of California, San
Diego)
Theocharis Theocharides (University of Cyprus)
Maria K. Michael (University of Cyprus)
