IEEE Computer
Society
Annual Symposium on VLSI, 2009
May 13-15, 2009, Tampa, Florida
Sponsored By:
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IEEE Computer
Society |
Sponsored By:
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         Sister Conference Great Lakes Annual Symposium on VLSI Design
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IEEE ISVLSI 2009: Accepted Submissions
A High Performance Unified BCD and Binary Adder/Subtractor Anshul Singh,Aman Gupta, Sreehari Veeramachaneni, M.B.Srinivas A High-Speed GCD Chip: A Case Study in Asynchronous Design Gennette Gill, John Hansen, Ankur Agiwal, Leandra Vicci and Montek Singh A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future Technologies Eduardo Rhod and Luigi Carro A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip Huaxi Gu, Kwai Hung Mo, Jiang Xu and Wei Zhang A New Placement Algorithm for Reduction of Soft Errors in Standard Cell Based Design of Nanometer Circuits Koustav Bhattacharya and Nagarajan Ranganathan A Non-uniform Grid based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient Venkateswaran N, Ravindhiran Mukundrajan, Mrigank Sharma and Badrinarayanan Ravi A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications Sungmin Bae, Ramakrishnan Krishnan and Vijaykrishnan Narayanan A Process Variation Tolerant Self-Compensating Sense Amplifier Design Aarti Choudhary and Sandip Kundu A Self-Reconfigurable Platform for Scalable DCT Computation using compressed Partial Bitstreams and BlockRAM Prefetching Jian Huang and Jooheung Lee Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Alexander and Vishwani Agrawal All Digital Dutycycle Correction Circuit in 90nm based on Mutex Swathi Ramasahayam and Srinivas M.B An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC Santanu Sarkar and Swapna Banerjee An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor Taecheol Oh, Hyunjin Lee, Kiyeon Lee and Sangyeun Cho An Efficient Hardware Architecture for Multimedia Encryption and Authentication using Discrete Wavelet Transform Amit Pande and Joseph Zambreno Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits Hassan Mostafa, Mohab Anis and Mohamed Elmasry Context-aware Post Routing Redundant Via Insertion Po-Heng Chu, Rung-Bin Lin, Da-Wei Hsu, Yu-Hsing Chen and Wei-Chih Tseng Design of Efficient Reversible Binary Subtractors Based on A New Reversible Gate Himanshu Thapliyal and Nagarajan Ranganathan Dual-Sum Single-Carry Self-Timed Adder Designs Balasubramanian P and Edwards D.A. Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems Weixun Wang and Prabhat Mishra Efficient Rerouting Algorithms for Congestion Mitigation M. A. R. Chaudhry, Z. Asad, A. Sprintson and J. Hu Energy-Efficient Encoding for High-Performance Buses with Staggered Repeaters Sharath Jayaprakash and Nihar Mahapatra Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs Hariharan Sankaran and Srinivas Katkoori Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding Roger Porto, Luciano Agostini and Sergio Bampi High Performance Crossbar Design in 3D Die-Stacking Technology Dean Lewis, Sudhakar Yalamanchili and Hsien-Hsin Lee High speed parallel architecture for cyclic convolution based on FNT Jian Zhang and Shuguo Li High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect Vijaya Sankara Rao Pasupureddi, Pradip Mandal and Sunil Sachdev HPAP: A High Performance Control Circuit for Asynchronous Pipeline Design Morteza Gholipour Geshnyani, Mehrdad Nourani, Doug Edwards and Ali Afzali-Kusha Improving the Efficiency of Charge Recovery Logic Using Body Biasing Mehrdad Khatir and Alireza Ejlali Increasing the Sensitivity of On-Chip Digital Thermal Sensors with Pre-Filtering Zhimin Chen, Raghunandan Nagesh, Anand Reddy and Patrick Schaumont Inducing Thermal-Awareness in Multi-Processor Systems-on-Chip Using Networks-on-Chip Emilio Martinez and David Atienza Leakage Power and Side Channel Security of Nanoscale Cryptosystem-on-Chip (CoC) Amir Khatib Zadeh and Catherine Gebotys Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd based platform FPGAs Prasanth Mangalagiri and Vijaykrishnan Narayanan Lossless Compression using Efficient Encoding of Bitmasks Chetan Murthy and Prabhat Mishra Low Cost and Memoryless CAVLD Architecture for H.264/AVC Decoder Thaķsa Silva, Joćo Alberto Vortmann, Luciano Agostini, Altamiro Susin and Sergio Bampi Low Phase-Noise and Wide Tuning-Range CMOS Differential VCO for Frequency Modulator Tuan Vu Cao, Dag T. Wisland, Tor Sverre Lande and Farshard Moradi Mapping Data and Code into Scratchpads from Relocatable Binaries Alexandre K. I. Mendonca, Daniel P. Volpato, Jose Luis Guntzel and Luiz C. V. Santos Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation Somayeh Timarchi, Keivan Navi and Omid Kavehei Modern floorplanning with boundary clustering constraints Li Li, Yuchun Ma, Ning Xu, Xianlong Hong and Yu Wang NoC Power Optimization Using a Reconfigurable Router Caroline Concatto, Debora Matos, Luigi Carro, Marcio Kreutz, Fernanda Kastensmidt and Altamiro Susin On-Line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise Yan Xu, Weichen Liu, Yu Wang, Jiang Xu, Xiaoming Chen and Huazhong Yang On-the fly evaluation of FPGA-based True Random Number Generator Renaud Santoro, Olivier Sentieys and Sébastien Roy Overview of the Scalable Communications Core: A Reconfigurable Wireless Baseband in 65nm CMOS Anthony Chun and Kyle McCanta Power-Efficient Body-Coupled Self-Cascode LC Oscillator for Low-Power Injection-Locked Transmitter Applications Mohammad Haider and Syed Islam Reduction of Current mismatch in PLL Charge Pump Shuaeb Fazeel, Leneesh Raghavan, Srinivasaraman Chandrasekaran and Manish Jain Scheduling for an Embedded Architecture with a Flexible Datapath Thomas Schilling, Magnus Själander and Per Larsson-Edefors Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design Debasri Saha and Susmita SurKoley Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs Hao Zheng, haiqiong Yao and Tomohiro Yoneda Synthesis-oriented scheduling of multiparty rendezvous in Transaction Level Models Vyas Venkataraman, Di Wang, Atabak Mahram, Wei Qin, Mrinal Bose and Jayanta Bhadra TEPS: Transient Error Protection Utilizing Sub-word Parallelism SeokIn Hong and Soontae Kim Testing Circuit-Partitioned 3D IC Designs Dean Lewis and Hsien-Hsin Lee The Ternary Quantum-dot Cellular Automata Memorizing Cell Primo˛ Pear, Miha Jane˛, Miha Mraz, Nikolaj Zimic and Iztok Lebar Bajec Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration Hai Li, Haiwen Xi, Yiran Chen, Xiaobin Wang and Tong Zhang Transition Inversion based Low Power Data Coding Scheme for Synchronous Serial Communication Bharghava Rajaram, Abinesh Ramachandran and Srinivas Mandalika Variation Aware Routing for Three-Dimensional FPGAs Chen Dong, Scott Chilstedt and Deming Chen
ISVLSI 2009 Web Chair Theo Theocharides (ttheocharides@ucy.ac.cy), University of Cyprus. |