IEEE Computer Society
 Annual Symposium on VLSI, Chennai, India,July 4-6, 2011

Home
Conference Location
Call For Papers
Committees
Important Dates
Paper Submission
PhD Forum
Program Schedule
Registration
Travel/Accommodation
Past Conferences

Sponsored By:

archiv1

 

 

FINAL PROGRAM SCHEDULE

 

Monday, July 4th, 2011  |  Tuesday, July 5th, 2011  |  Wednesday, July 6th, 2011

 

Click Here for the PDF Version

 


 

Final Program for ISVLSI 2011

MONDAY July 4, 2011

8:00 am -

Registration

8:15 – 8:30am

Inauguration

8:30-10:00 am

M1A: FPGAs 

Chair: Juergen Becker

l  Feasibility Study of Using RF Interconnects in Large FPGAs to Improve Routing Tracks Usage - Adel Dokhanchi, Ali Jahanian, Esfandiar Mehrshahi and Mohammad Taghi Taimoori

 

l  High Level Power Estimation Models for FPGAs - Avinash Lakshminarayana, Sumit Ahuja and Sandeep Shukla

 

l  The Study of a Dynamic Reconfiguration Manager for Systems-on-Chip - Matthias Kuehnle, Alisson Brito, Christoph Roth, Konstantinos Dagas and Juergen Becker

M1B: 3D ICs

Chair: Jiang Xu

l  A Low-overhead Fault-aware Deflection Routing Algorithm for 3D Network-on-Chip - Chaochao Feng, Minxuan Zhang, Jinwen Li, Jiang Jiang, Zhonghai Lu and Axel Jantsch

 

l  Physical Implementation of an Asynchronous 3D-NoC Router using Serial Vertical Links - Florian Darve, Abbas Sheibanyrad, Pascal Vivet and Frιdιric Petrot

 

l  Optimizing Test Wrapper for Embedded Cores using TSV based 3D SOCs - Surajit Kumar Roy, Chandan Giri, Sourav Ghosh and Hafizur Rahaman

10:00 – 10:15am

TEA BREAK

10:15 – 11:10 am

M1K: Chair: Susmita Sur-Kolay

Solutions and Challenges in Modern Circuit Placement – SLIDES

Prof. Yao-Wen Chang, National Taiwan University  

11:15 – 12:45 pm

M2A: Nanoelectronics

Chair: T R Ramachandran

l  Effect of Gate-S/D Underlap, Asymmetric and Independent Gate features in the minimization of Short Channel Effects in Nanoscale DGMOSFETs – Ramesh Vaddi, S. Dasgupta and R. P. Agarwal

 

l  Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits - Ganesh C. Patil and Shafi Qureshi

 

l  An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance - Shashank Parashar, Chaudhry Indra Kumar and Manisha Pattanaik

M2B: Network-on-Chips

Chair: Arcot Sowmya

l  A DRAM Centric NoC Architecture and Topology Design Approach - Ciprian Seiculescu, Srinivasan Murali, Luca Benini and Giovanni De Micheli

 

 

l  A Method for Integrating Network on Chip Topologies with 3D ICs – M. Pawan Kumar, Anish S. Kumar, Srinivasan Murali, Luca Benini and Kamakoti Veezhinathan

 

l  A NoC Traffic Suite Based on Real Applications - Weichen Liu, Jiang Xu, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Wei Zhang, Mahdi Nikdast and Zhehui Wang

12:45 – 1:30pm

LUNCH

1:30 – 3:00 pm

M3A: Mixed Signal Design

Chair: TBA

l  500 MHz Delay lock based 128-bin, 256 ns deep analog memory ASIC "Anusmriti"

- Menka Sukhwani, Vinay Chandratre, Megha Thomas, Chandrakant Pithwa and Vangmayee Sharda,

 

l  A 16-Gbps 9mW Transmitter With FFE in 90nm CMOS Technology for Off-Chip Communication

 - Saurabh Sant, Sandeep Waikar, Marshnil Dave, Maryam Shojaei Baghini and Dinesh Sharma

 

l  A Response Surface Method for Design Space Exploration and Optimization of Analog Circuits

 - Arnab Khawas, Amitava Banerjee and Siddhartha Mukhopadhyay

M3B: Placement

Chair: Yao-Wen Chang

l  A New Wirelength Model for Analytical Placement – B. N. B. Ray and Shankar Balachandran

 

 

 

 

 

l  Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement - Yiqiang Sheng, Atsushi Takahashi and Shuichi Ueno

 

 

 

l  Statistical Timing-based post-Placement Leakage Recovery - Evriklis Kounalakis, Christos Sotiriou and Vassilis Zebilis

3:05 – 4:00 pm

M2K: Chair: Sri Parameswaran

Reliability of On-Chip Systems – A Thermal Perspective - SLIDES

Prof. Joerg Henkel, Karlsruhe Institute of Technology 

4:00 – 4:15pm

TEA BREAK

4:15 – 5:15 pm

MP1: Chair: Shankar Balachandran

l  Verification of Register Transfer Level Low Power Transformations - Chandan Karfa, C. Mandal and D. Sarkar

 

l  Gate Sizing Minimizing Delay and Area  - Gracieli Posser, Guilherme Flach, Gustavo Wilke and Ricardo Reis

 

l  A Group-Preferential Parallel-Routing Algorithm for Cross-referencing Digital Microfluidic Biochips  -  Pranab Roy, Rajesh Mandal, Hafizur Rahaman and Parthasarathi Dasgupta

 

l  Post-Synthesis Circuit Techniques for Runtime Leakage Reduction - Seetal Potluri, Nitin Chandrachoodan and Kamakoti Veezhinathan

 

l  A Global optimization for Scan Chain Insertion at RT-Level - Lilia Zaourar, Yann Kieffer and Chouki Aktouf

 

l  High Speed Convolution and Deconvolution using Urdhva Tiryagbhyam - Rashmi Lomte and Pradip Bhaskar

 

MP2: Chair: TBA

l  A Design of Experiment based Approach to Variance Optimal Design of CMOS OpAmp - Arnab Khawas and Siddhartha Mukhopadhyay

 

l  An Analytical Drain Current Model for Short-channel Triple-material Double-gate MOSFETs - Harshit Agnihotri, Abhishek Ranjan, Pramod Kumar Tiwari and S. Jit

 

l  Design to Introduce On-Chip Fine Tunability in Analog Active Inductor - Garima Kapur, Kapil Bhola and C.M Markan

 

l  On the Potentials of FinFETs for Asynchronous circuit Design - Fataneh Jafari, Mahdi Mosaffa and Siamak Mohammadi

 

l  Modeling Study of Impact of Surface Roughness on Flicker Noise in MOSFET - Prafulla Galphade and Rasika Dhavse

5:15 - 6:15pm

Ph D Forum: Chair: Nitin Chandrachoodan & Juergen Becker

l  Power-Efficient Inter-Layer Communication Architectures for 3D NoC - Amir-Mohammad Rahmani, Khalid Latif, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila and Hannu Tenhunen.

 

l  Design and Evaluation of Mesh-of-Tree based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits - Santanu Kundu and Santanu Chattopadhyay.

 

l  Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier  - Deepak Dasalukunte, Fredrik Rusek, John. B Anderson and Viktor Owall

 

l  Synthesis of Analog IC Building Blocks - Alpana Agarwal and Chandra Shekhar Sharma

 

l  Design and Analysis of Pairing Based Cryptographic Hardware for Prime Fields - Santosh Ghosh

 

l  Study and Analysis of Power Optimization Techniques for Embedded Systems - G. Indumathi and K V Ramakrishnan.

 

l  Next Generation Smart Home Systems using Hardware Acceleration - David Fuschelberger, Ioannis Pyrounakis, Anastasios Dagiuklas, Nikolaos Voros and Carlos Ribeiro

 

l  Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family - Chia-I Chen and Juinn-Dar Huang

 

l  Thermal Analysis of 3D stacked systems - Kameswar Rao Vaddina, Amir-Mohammad Rahmani, Khalid Latif, Pasi Liljeberg and Juha Plosila

7:00 – 8:00 pm

CULTURAL PROGRAM

TUESDAY July 5, 2011

8:30-9:30 am

T1A :VLSI Circuits

Chair: TBA

l  A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz - Arnab Kumar Biswas, Anand Bulusu and Sudeb Dasgupta

 

l  Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC - Manas Kumar Hati and Tarun K. Bhattacharyya

T1B: Reversible Logic

Chair: Hafizur Rahaman

l  ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization - Robert Wille, Hongyan Zhang and Rolf Drechsler

 

l  Design of a Reversible ALU based on Novel Programmable Reversible Logic Gate Structures - Matthew Morrison and Nagarajan Ranganathan

9:35 – 11:00 am

T1K: Chair: Vijaykrishnan Narayanan

l  The Light at the end of the CMOS Tunnel – Dr. Sani Nassif, IBM

SLIDES

l  Scaling Product Execution: Addressing the Challenges of Growth – Dr. T. R. Ramachandran, LSI

SLIDES

11:00 – 11:15am

TEA BREAK

11:15 – 12:45 pm

T2A: Clock Network design

Chair: Atsushi Takahashi

l  A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology - Naveen Kumar Kancharapu, Marshnil Dave, Maryam Shojaei Baghini and Dinesh K Sharma

 

l  A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing - Zohre Mohammadi-Arfa and Ali Jahanian

 

l  Layer-Aware Design Partitioning for Vertical Interconnect Minimization - Ya-Shih Huang, Yang-Hsiang Liu and Juinn-Dar Huang

T2B: Verification

Chair: Virendra Singh

l  Requirement Evolution Management: A systematic approach - Ansuman Banerjee

 

 

l  Equivalence Checking of Array-Intensive Programs - Chandan Karfa, Kunal Banerjee, Dipankar Sarkar and Chittaranjan Mandal

 

l  Application of formal methods for system-level verification of Network on Chip - Vinitha Arakkonam Palaniveloo, Sowmya Arcot and Sridevan Parameswaran

12:45 – 1:30pm

LUNCH

1:30 – 3:00 pm

T3A: Low Power 1

Chair: Joerg Henkel

l  A Markov Performance Model for Buffered Protocol Design - Jing Cao and Albert Nymeyer

 

l  Low Power Motion Estimation with Probabilistic Computing - Charvi Dhoot, Vincent Mooney, Lap Pui Chau and Shubhajit Roy Chowdhury

 

l  Low Power Probabilistic Floating Point Multiplier Design - Aman Gupta, Satyam Mandavalli, Vincent J. Mooney, Keck-Voon Ling, Arindam Basu, Henry Johan and Budianto Tandianus

T3B: Physical Design

Chair: Ricardo Reis

l  TSV-Aware Scan Chain Re-ordering for 3D ICs - Ayan Datta, Charudhattan Nagarajan and Susmita Sur Kolay

 

l  Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs - Michael Buttrick and Sandip Kundu

 

l  Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability - Nishant Dhumane, Sudheendra K. Srivathsa and Sandip Kundu

3:15 – 9:00pm

TOUR & BANQUET

WEDNESDAY July 6, 2011

8:30-10:00 am

W1A: Interconnect

Chair: Sridhar Rangarajan

l  A Simulation based Buffer Sizing Algorithm for Network on Chip - Anish Kumar, M. Pawan Kumar, Srinivasan, Murali, Kamakoti Veezhinathan, Luca Benini, and Giovanni De Micheli

 

l  Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment - Shuzhe Zhou, Hailong Yao, Qiang Zhou and Yici Cai

 

l  Enhanced Redundant Via Insertion with Multi-Via Mechanisms - Ting-Feng Chang, Tsang-Chi Kan, Shih-Hsien Yang and Shanq-Jang Ruan

W1B: Security

Chair: N. Voros

l  Design of Unique and Reliable Physically Unclonable Functions based on Current Starved Inverter Chain - Raghavan Kumar, Vinay C Patil and Sandip Kundu

 

l  Impact of Circuit Degradation on FPGA Design Security - Han-Wei Chen, Suresh Srinivasan, Yuan Xie and Vijaykrishnan Narayanan

 

l  Towards Resilient Micro-Architectures: Datapath Reliability Enhancement using STT-MRAM - Karthik Swaminathan, Ravindhiran Mukundrajan, Niranjan Soundararajan and Vijaykrishnan Narayanan

10:00 – 10:15am

TEA BREAK

10:15 – 11:10 am

W1K: Chair: Amar Mukherjee

The Variability Expeditions: Exploring the Software Stack for UNderdesigned Computing Mchines – Prof. Rajesh Gupta, U. California at San Diego

SLIDES

11:15 – 12:45 pm

W2A: Emerging Technologies

Chair: V. Kamakoti

l  Metallic-CNT and Non-uniform CNTs Tolerant Design of CNFET-based Circuits using Independent N2-Transistor Structures - Behnam Ghavami, Mohsen Raji and Hossein Pedram

 

l  On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements - Vikram Suresh, Priyamvada Vijayakumar and Sandip Kundu

 

l  Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip - Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang and Weichen Liu

W2B: System Level Synthesis

Chair: TBA

l  A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC - Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast and Zhehui Wang

 

l  Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors - Li Tang, Shuai Wang, Jie Hu and Xiaobo Sharon Hu

 

l  AIFSP: An Adaptive Instruction Flow Stream Processor - Yaohua Wang, Shuming Chen, Jianghua Wan, Kai Zhang and Shenggang Chen

12:45 – 1:30pm

LUNCH

1:30 – 3:00 pm

W3A: Low Power 2

Chair: Sandip Kundu

l  A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis - Sharad Sinha, Udit Dhawan, Siew Kei Lam and Thambipillai Srikanthan

 

l  Power Efficient Multiplexer using DLDFF Synchronous Counter – P. Rajshekar and M. Malathi

 

l  A Novel Evolutionary Technique for Multi-Objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths – D. S. Harish Ram, M. C. Bhuvaneswari an S. M. Logesh

W3B: High Level Synthesis

Chair: Rajesh Gupta

l  Improved Memory Architecture for Multicarrier Faster-than-Nyquist Iterative Decoder - Deepak Dasalukunte, Fredrik Rusek and Viktor Owall

 

l  Application-Specific Energy Optimization of General-Purpose Datapath Interconnect - Babak Hidaji, Salar Alipour, Kasyab Parmesh Subramaniyan and Per Larsson-Edefors

 

l  Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID system in Quaternary Domain. -  Varun Vasudevan, Vinay Sheshadri, Sivarama Krishnan R. and Vasundara Patel K. S.

3:05 – 4:00 pm

WP1: Chair: TBA

·         Application Mapping onto Mesh Structured Network-on-Chip using Particle Swarm Optimization - Pradip Kumar Sahu, Putta Venkatesh, Sunilraju Gollapalli and Santanu Chattopadhyay

 

·         Pre-processing based Run-Time  Mapping of Applications on NoC-based MPSoCs - Samarth Kaushik, Amit Kumar Singh and Thambipillai Srikanthan

 

·         A Design Space Exploration Methodology for Application Specific MPSoC Design - Amit Kumar Singh, Akash Kumar and Thambipillai Srikanthan

 

·         Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis - Soumya J, Putta Venkatesh and Santanu Chattopadhyay

 

  • Intelligent On/Off Link Management for On-Chip Networks - Andreas Savva, Theocharis Theocharides and Vassos Soteriou

WP2: Chair: Madhu Mutyam

·         Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design - Mallikarjuna Rao Nimmagadda and Ajit Pal

 

·         Efficient VLSI Architectures for the Hadamard Transform Based on Offset-Binary Coding and ROM Decomposition – B. Sandeep Kumar, Vikramkumar Pudi and K. Sridharan

 

·         A Prefix Based Reconfigurable Adder - V.  Chetan Kumar, P. Sai Phaneendra, S. Ershad Ahmed,  Sreehari Veeramachaneni, N. Moorthy Muthukrishnan an M. B. Srinivas

 

·         Architectures for Simultaneous Coding and Encryption Using Chaotic Maps - Amit Pande, Joseph Zambreno and Prasant Mohapatra

 

  • Low Power Asynchronous Sigma-Delta Modulator using Hysteresis Level Control - Anita Arvind Deshmukh, Raghavendra Deshmukh and Rajendra Patrikar

4:15 – 5:00 pm                   

Panel discussion/ Valedictory


 

 

This site is maintained by:
ISVLSI 2011 Web Chairs

Soontae Kim (kims@kaist.ac.kr), Korea Advanced Institute of Science and Technology
Theo Theocharides (ttheocharides@ucy.ac.cy), University of Cyprus.