ISVLSI 2020 explores emerging trends and novel ideas and concepts in the area of VLSI. The symposium covers a range of topics: from VLSI circuits, systems and design methods to system-level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies such as security, artificial intelligence and cyber-physical systems. The symposium will also emphasize future design methodologies and new CAD tools to support them as key topics. Over three decades ISVLSI has been a unique forum promoting multidisciplinary research and new visionary approaches in the area of VLSI, bringing together leading scientists and researchers from academia and industry. The ISVLSI proceedings will be published by IEEE Computer Society Press. Selected papers from past editions have been subsequently published in special issues of top archival journals. ISVLSI has a good reputation of bringing together well-known international scientists as invited speaks. ISVLSI 2020 will continue the momentum and carry forward these well-established trends for further growth of the symposium.
Contributions are sought in, but not limited to, the Following Tracks
1) Circuits, Reliability, and Fault-Tolerance (CRT): Analog/mixed-signal circuits design and testing, RF and communication circuits, design for testability and reliability, adaptive circuits, interconnects, static and dynamic defect-and fault-recoverability, and variation-aware design.
2) Computer-Aided Design and Verification (CAD): Hardware/software co-design, logic and behavioral synthesis, simulation and formal verification, physical design, signal integrity, power and thermal analysis , statistical approaches.
3) Digital Circuits and FPGA based Designs (DCF): Digital circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits, energy efficient circuits, near and sub-threshold circuits, memories, FPGA designs, FPGA based systems.
4) Emerging and Post-CMOS Technologies (EPT): Nanotechnology, molecular electronics, quantum devices, optical computing, spin-based computing, biologically-inspired computing, CNT, SET, RTD, QCA, reversible logic, and CAD tools for emerging technology devices and circuits.
5) System Design and Security (SDS): Structured and Custom Design methodologies, microprocessors/micro-architectures for performance and low power, embedded processors, analog/digital/mixed-signal systems, NoC, power and temperature aware designs, Hardware security, Cryptography, watermarking, and IP protection, TRNG and security oriented circuits, PUF circuits.
6) VLSI for Applied and Future Computing (AFC): Neuromorphic and brain-inspired computing, quantum computing, circuits and architectures for machine learning and artificial intelligence, methodologies for on-chip learning, deep learning acceleration techniques, applications for and use-cases of learning systems, sensor and sensor network, electronics for Internet of Things and smart medical devices.
The Symposium Program will include contributed papers and speakers invited by the Program Committee as well as a poster session. Keynotes, panels, special sessions and a Student Research Forum are planned as well. Taking place in Europe, the Symposium will also include sessions and forums dedicated to European research projects. Authors are invited to submit full-length, original, unpublished manuscripts in PDF format (up to 6 pages), omitting author information details.
Questions and Requests, please contact the
Submission: Authors are invited to submit full-length (6 pages maximum), original, unpublished papers along with an abstract of at most 200 words (IEEE Standard Template - Font Size 10pt). To enable blind review, the author list should be omitted
from the main document. Papers violating length and blind-review
criteria would be withdrawn from the review process. Previously
published papers or papers currently under review for other
conferences/journals should not be submitted and will not be considered
Paper Submission Deadline:
2020 (Abstract) / March 27, 2020 (Final Submission)
Acceptance Notification: May 10, 2020
Submission of Final Version: May 25, 2020