IEEE Computer Society Annual Symposium on VLSI
Aliathon Resort, Pafos, Cyprus, July 4-6, 2022

Qries Qries

Plenary Talks are at the bottom part of this page. You can click here to view them.  

Keynote Speakers


 Monday Morning Plenary Keynote

Giacomo Indiveri

Professor at the Faculty of Science of the University of Zurich and at Department of Information Technology and Electrical Engineering of ETH Zurich

Neuromorphic Intelligence: Electronic circuits for emulating neural processing systems, and their application to extreme-edge computing.


Artificial Intelligence (AI) and deep learning algorithms have demonstrated impressive results in a wide range of applications. However, they still have serious shortcomings for use cases that require real-time processing of sensory data and closed-loop interactions with the real-world, in uncontrolled environments.
Neuromorphic Intelligence (NI) aims to mitigate this shortcoming by developing ultra-low power electronic circuits and radically different brain-inspired in-memory computing architectures.
In this presentation I will present examples of NI circuits that exploit the physics of their devices to directly emulate the biophysics of real neurons, and I will demonstrate applications of NI processing systems to use cases that require low power, local processing of the sensed data, and that cannot afford to connect to the cloud for running AI algorithms.  

Short Bio

Giacomo Indiveri is a dual Professor at the Faculty of Science of the University of Zurich and at Department of Information Technology and Electrical Engineering of ETH Zurich, Switzerland. He is the director of the Institute of Neuroinformatics of the University of Zurich and ETH Zurich. He obtained an M.Sc. degree in electrical engineering in 1992 and a Ph.D. degree in computer science from the University of Genoa, Italy in 2004.
Engineer by training, Indiveri has also expertise in neuroscience, computer science, and machine learning. He has been combining these disciplines by studying natural and artificial intelligence in neural processing systems and in neuromorphic cognitive agents. His latest research interests lie in the study of spike-based learning mechanisms and recurrent networks of biologically plausible neurons, and in their integration in real-time closed-loop sensory-motor systems designed using analog/digital circuits and emerging memory technologies. His group uses these neuromorphic circuits to validate brain inspired computational paradigms in real-world scenarios, and to develop a new generation of fault-tolerant event-based neuromorphic computing technologies. Indiveri is senior member of the IEEE society, and a recipient of the 2021 IEEE Biomedical Circuits and Systems Best Paper Award. He is also an ERC fellow, recipient of three European Research Council grants.


 Tuesday Morning Plenary Keynote

Vijay Narayanan

Robert Noll Chair of Computer Science and Engineering at The Pennsylvania State University

Recent Advances in Ferroelectric-based Logic and Memory Architectures


In the last decade, there have been major changes in the families of ferroelectric materials available for integration with CMOS electronics. This talk will discuss the possibility of exploiting the 3rd dimension in microelectronics for functions beyond interconnect optimization, enabling 3D non-von Neumann computer architectures exploiting ferroelectrics for local memory, logic in memory, digital/analog computation, and neuromorphic/reconfigurable functionality. This approach circumvents the end of Moore's law in 2D scaling, while simultaneously overcoming the "von Neumann bottleneck" in moving instructions and data between separate logic and memory circuits. The talk will cover circuit and architectural features leveraging the non-volatile properties of ferro-electric FETs for hardware obfuscation, accelerator designs and in-memory compute structures.  

Short Bio

Vijaykrishnan Narayanan is the Robert Noll Chair of Computer Science and Engineering at The Pennsylvania State University. His research interests are in computer architecture, design using emerging technologies, and embedded systems. He is a recipient of the 2021 IEEE Computer Society Edward McCluskey Technical Achievement Award, and 2021 IEEECS TCVLSI Distinguished Research Award. He serves as the Associate Director of the DoE 3DFeM Center. His work is funded by DARPA/SRC JUMP Centers (CRISP and CBRIC) and National Science Foundation. He is a Fellow of the IEEE, ACM and National Academy of Inventors.


 Wednesday Morning Plenary Keynote

Elisabetta Farella

Head of the Energy Efficient Embedded Digital Architectures (E3DA) unit at the Fondazione Bruno Kessler in Trento, Italy

TinyML for tiny embedded systems


In the Internet of Things (IoT) era, where we see many interconnected and heterogeneous mobile and fixed smart devices, distributing intelligence from the cloud to the edge has become critical for the sustainability of the infrastructures. A distributed approach also comes with additional benefits (e.g. power efficiency, low-latency inference, privacy-by-design) with respect to centralized cloud computing. TinyML is an emerging field that has gained much traction in the last few years. This paradigm brings novel challenges to the embedded systems domain, particularly when we aim to perform deep learning at the "very edge" on IoT end devices, where limited resources are available. In this presentation, I will propose some of the research done at E3DA to tackle the TinyML challenges for energy-efficient embedded devices. Our primary focus is on multimedia analytics at the edge and privacy-by-design systems. Our efforts landed in state-of-the-art audio and video analytics performance, namely in sound event detection and multi-object detection and tracking with a fraction of the computational complexity of the previous state-of-the-art approaches. Moreover, we developed a novel approach to generate deep fakes for privacy-by-design applications directly at the edge.  

Short Bio

Elisabetta Farella, Ph.D., is the lead researcher of the Energy Efficient Embedded Digital Architectures (E3DA) unit at the Fondazione Bruno Kessler in Trento, Italy. Her research is in the field of energy-independent embedded systems that are, at the same time, equipped with artificial on-board intelligence. Examples of such systems are Wireless Sensor Networks, wearable electronics, Internet of Things from the point of view of devices equipped with smart sensors and actuators. These technologies are used in various application fields from motor rehabilitation to human-machine interaction, especially in smart cities and communities. She worked since 2014 as coordinator of the research activities on-body sensor and actuators networks, smart objects and tangible interfaces at the Department of Electrical, Electronic and Information Engineering (DEI) at the University of Bologna ( within the group of Prof. Luca Benini. From Spring 2001 to end of 2005 she was research fellow at CINECA Visit Lab ( From 2006 to 2010 she was research supervisor at T3lab ( of 3 groups of researchers working on embedded systems (wireless sensor networks, ambient assisted living, RFID). Elisabetta participates with different roles in several National and International projects (e.g. EU projects), cooperating with industries and academies.


Plenary Talks


Onur Mutlu

Professor of Computer Science at ETH Zurich

Memory-Centric Computing


Computing is bottlenecked by data. Large amounts of application data overwhelm storage capability, communication capability, and computation capability of the modern machines we design today. As a result, many key applications' performance, efficiency and scalability are bottlenecked by data movement. In this lecture, we describe three major shortcomings of modern architectures in terms of 1) dealing with data, 2) taking advantage of the vast amounts of data, and 3) exploiting different semantic properties of application data. We argue that an intelligent architecture should be designed to handle data well. We show that handling data well requires designing architectures based on three key principles: 1) data-centric, 2) data-driven, 3) data-aware. We give several examples for how to exploit each of these principles to design a much more efficient and high performance computing system. We especially discuss recent research that aims to fundamentally reduce memory latency and energy, and practically enable computation close to data, with at least two promising novel directions: 1) processing using memory, which exploits analog operational properties of memory chips to perform massively-parallel operations in memory, with low-cost changes, 2) processing near memory, which integrates sophisticated additional processing capability in memory controllers, the logic layer of 3D-stacked memory technologies, or memory chips to enable high memory bandwidth and low memory latency to near-memory logic. We show both types of architectures can enable orders of magnitude improvements in performance and energy consumption of many important workloads, such as graph analytics, database systems, machine learning, video processing. We discuss how to enable adoption of such fundamentally more intelligent architectures, which we believe are key to efficiency, performance, and sustainability. We conclude with some guiding principles for future computing architecture and system designs.

A short accompanying paper, which appeared in DATE 2021, can be found here and serves as recommended reading:

A longer overview & survey of modern memory-centric computing can be found here and also serves as recommended reading: "A Modern Primer on Processing in Memory"  

Short Bio

Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the Intel Outstanding Researcher Award, IEEE High Performance Computer Architecture Test of Time Award, NVMW Persistent Impact Prize, the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, ACM SIGARCH Maurice Wilkes Award, the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, US National Science Foundation CAREER Award, Carnegie Mellon University Ladd Research Award, faculty partnership awards from various companies, and a healthy number of best paper or "Top Pick" paper recognitions at various computer systems, architecture, and security venues. He is an ACM Fellow "for contributions to computer architecture research, especially in memory systems", IEEE Fellow for "contributions to computer architecture research and practice", and an elected member of the Academy of Europe (Academia Europaea). His computer architecture and digital logic design course lectures and materials are freely available on YouTube (, and his research group makes a wide variety of software and hardware artifacts freely available online ( For more information, please see his webpage at


 ISVLSI 2022 Embedded Tutorial

Ricardo Reis

Professor at the Instituto de Informatica of the Universidade Federal do Rio Grande do Sul (UFRGS)

VLSI Design Optimization


The always increasing transistor count in modern chips, as well the exploding number of devices connected to the internet of things, is demanding new design approaches. One fundamental issue and challenge is the design optimization, mainly power optimization. In some applications, as implantable devices, reliability and power optimization is fundamental. It will be done an overview of some techniques for power optimization at different levels of abstraction. But the main focus will be related to the physical design optimization, as it is becoming an important issue, not only for power optimization, but also for connections and vias optimization, increasing routability as well reliability. It will be shown techniques and examples of optimization at physical design level.  

Short Bio

Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 700 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011). He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011, 2012, and 2018, and R9 Chapter of The Year 2013, 2014, 2016, 2017 and 2020. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. He also started with the EMicro, an annually microelectronics school in South Brazil. In 2002 he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society). He was member of CASS DLP Program (2014/2015), and he has done more than 70 invited talks in conferences. Member of IEEE CASS BoG and IEEE CEDA BoG. Member of the IEEE IoT Initiative Activity Board. Chair of the IEEE CASS SiG on IoT. Ricardo received the IFIP Fellow Award. He also received the ACM/ISPD Lifetime Achievement Award 2022.





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