TECHNICAL AREAS

Analog and Mixed-Signal
Test:
Haralampos Stratigopoulos,
TIMA Labs,
haralampos.stratigopoulos@imag.fr
 

Biomedical Devices and Applications
Mohammad Sawan
Ecole Polytechnique de Montreal;
sawan@polymtl.ca

CAD for Low-Power Design
Massimo Poncino,
Politechnico di Torino;
Massimo.poncino@polito.it

Deep-Submicron Design, EDA,
and Technology:
Vivek De, Intel;
vivek.de@intel.com

Defect-Based Test:

Adit Singh,
Auburn University;
adsingh@eng.auburn.edu
 

DFM and Yield:

Anne E. Gattiker,
IBM;

gattiker@us.ibm.com

Design-for-Testability
Rubin Parekhji, Teaxs Instruments (India);
parekhji@ti.com

Economics of Design
and Test:

Magdy Abadir,
Freescale Semiconductor;
m.abadir@freescale.com

Embedded Real-Time Systems:
Prabhat Mishra, University
of Florida;

prabhat@cise.ufl.edu

Emerging Technologies (Bio & Nano):
Mircea Stan,
University of Virginia;
mircea@virginia.edu

Cyber-Physical Systems:

Paul Bodgan, USC;
paulbogdan2010@gmail.com

Hardware Trust and Secure
ICs:

Ramesh Karri,
NYU Polytechnic School of Engineering;
rkarri@nyu.edu

Interconnect Technologies:
Partha Pratim Pande, Washington State University;
pande@eecs.wsu.edu

Low Power Systems and Green Computing:
Anand Raghunathan,
Purdue University;
raghunathan@purdue.edu

Memory Design and Test:
Cheng-Wen Wu, National Tsing Hua
University;

cww@ee.nthu.edu.tw
 

Said Hamdioui, TU Delft, Netherlands

S.Hamdioui@tudelft.nl

MultiCore for High Performance and Ultra-Low Power:
David Atienza
EPFL;
David.atienza@epfl.ch

Networks on Chip:
Umit Ogras,
Arizona State University;
umit@asu.edu

Online Test and Fault Tolerance:
Qiang Xu,

Chinese University of
Hong Kong;

 qxu@cse.cuhk.edu.hk

Physical Design Automation:
Sung Kyu Lim, Georgia Tech;
limsk@ece.gatech.edu

Reconfigurable Embedded
Systems:

Jan Madsen,

Technical University of Denmark;
jan@imm.dtu.dk

Silicon Debug:

Nicola Nicolici,
McMaster University;
nicola@ece.mcmaster.ca

SoC Testing:
Erik Jan Marinissen, IMEC;
erik.jan.marinissen@imec.be
 

Asynchronous Design:
Steven Nowick, Columbia University;
nowick@cs.columbia.edu

System-Level Design and Optimization
Petru Eles
Linkoping University;
Petru.eles@liu.se


Digital and Mixed-Signal Verification, Post Silicon Validation:
Shobha Vadusevan, UIUC;
shobhav@illinois.edu

 

Reliable, Secure, and Energy-Efficient Design:

Sanghamitra Roy, Utah State University;

sanghamitra.roy@usu.edu

DEPARTMENTS

Book Reviews:

Scott Davidson,

Oracle,

scott.davidson@oracle.com;

Grant Martin, Tensilica,

gmartin@ieee.org;

Igor Markov, University of Michigan,

igor.markov1@gmail.com

CEDA Currents:

Rajesh K. Gupta,

University of California, San Diego;

gupta@cs.ucsd.edu

Reports and Summaries:

Yervant

Zorian, Synopsys;

yervant.zorian@synopsys.com

DATC Newsletter:

Joe Damore,

joepdamore@aol.com

Interviews:

Erik Jan Marinissen, IMEC

mariniss@imec.b

The Last Byte:

Scott Davidson,

Oracle;

scott.davidson@oracle.com

Perspectives:

Rajesh K. Gupta,

University of California, San Diego,

gupta@cs.ucsd.edu;

Yervant Zorian, Synopsys,

yervant.zorian@synopsys.com

The Road Ahead:

Andrew Kahng, University of California,

San Diego; abk@ucsd.edu

Roundtables:

David Yeh, SRC;

david.yeh@src.org

Standards (Design):

Stan Krolikoski, Cadence Design

Systems;

stanleyk@cadence.com

Standards (Test):

Bill Eklow, Cisco;

beklow@cisco.com

TTTC Newsletter:

Theo Theocharides, University of Cyprus;
ttheocharides@ucy.ac.cy

Tutorials:

Dimitris Gizopoulos,

University of Athens;

dgizop@di.uoa

General Column Editor:
 

Theo Theocharides, University of Cyprus;
ttheocharides@ucy.ac.cy

D&T Alliance Program

DTAP chair:

Yervant Zorian, Synopsys;

yervant.zorian@synopsys.com

Asia:

Hidetoshi Onodera, Kyoto

University;
onodera@i.kyoto-u.ac.jp

DAC:

Andrew Kahng,

University of California, San Diego;

abk@ucsd.edu

DATC:

Joe Damore;

joepdamore@aol.com

DATE:

Ahmed Jerraya, CEA-LETI;

ahmed.jerraya@cea.fr

Europe:

Bernard Courtois, TIMA-CMP;

bernard.coourtois@imag.fr

Latin America:

Ricardo Reis,

Universidade Federal do Rio

Grande do Sul;

reis@inf.ufrgs.br

TTTC:

Michael Nicolaidis

TIMA;

michael.nicolaidis@tima.fr

IEEE PRODUCTION STAFF

IEEE Periodicals/Magazines Department

445 Hoes Lane, Piscataway,

NJ 08854 USA

Phone: +1 732 562 3950,

Fax: +1 732 981 1855

www.ieee.org/magazines

Senior Managing Editor

William A. Colacchio,

w.colacchio@ieee.org

Managing Editor

Jessica Barrague

j.barrague@ieee.org

Senior Managing Editor

Geraldine Krolin-Taylor,

g.krolin-taylor@ieee.org

Senior Art Director

Janet Dudar,

j.dudar@ieee.org

Assistant Art Director

Gail A. Schnitzer,

g.schnitzer@ieee.org

Production Coordinator

Theresa L. Smith,

tlsmith@ieee.org

Production Director

Peter M. Tuohy,

p.tuohy@ieee.org

Advertising Production Manager

Felicia Spagnoli,

f.spagnoli@ieee.org

Editorial Director

Dawn Melley,

d.melley@ieee.org

Staff Director, IEEE Publishing Operations

Fran Zappulla

f.zappulla@ieee.org

Cover Design

Alex Torres