A/A |
Date |
Laboratory
Details |
Assignments |
Report Due
Date |
| 1.1 |
3(or 4)/9/2007
In LA 130 |
Software Lab 1.
Introduction to Altera MAX +Plus Logic Design Tool |
Max
+Plus Tutorial (Greek) |
|
| 1.2 |
10(or 11)/9/2007
In LA 132 |
Hardware Lab 1.
Introduction to Logic Hardware -- AND, OR, and NOT gates.
|
Hardware
Lab 1 (Greek) |
+7 days from
Assignment |
| 2.1 |
17(or 18)/9/2007
In LA 130 |
Software Lab 2.
Introduction to NAND, NOR and XOR Gates. Design of Multiple-Switch
Lamp Controls. |
Software/Hardware Lab 2 (Greek) |
|
| 2.2 |
24(or 25)/10/2007
In LA 132 |
Hardware Lab 2.
Implementation of NAND, NOR and XOR Gates (with PLDs and discrete
components). Testing and Verification. |
|
+7 days from
Assignment |
| 3.1 |
1(or 2)/10/2007
In LA 130 |
Software Lab 3.
Combinational design using multiplexers and decoders. Design
of adders/subtractors. |
Software
Lab 3 (Greek)
(necessary
files) |
Together with Hardware Laboratory 3. |
| 3.2 |
8(or 9)/10/2007
In LA 132 |
Hardware Lab 3.
Implementation of 4-bit full Adder/Subtractor with PLDs. Implementation
of 1-bit full Adder with multiplexers and decoders, using
discrete components. Testing and Verification. |
Hardware
Lab 3 (Greek)
(UP2 Core Library Functions) |
+7 days from
Assignment |
| 4.0 |
15(or 16)/10/2007
In LA 130 |
Lecture: Binary Memory Units and Ripple Counters |
pdf ppt |
|
| 4.1 |
22(or 23)/10/2007
In LA 130 |
Midterm Exam
Software Lab 4.
Binary Memory Units: SR Latch, D and JK Flip-Flops. Design
of a modulo 16/10 Ripple Counter. |
Software/Hardware
Lab 4 (Greek)
(necessary
files) |
|
| 4.2 |
29(or 30)/10/2007
In LA 132 |
Hardware Lab 4.
Implementation of a modulo 16/10 Ripple Counter with PLDs.
Implementation a modulo 16/10 Ripple Counter with flip-flops,
using discrete components. Testing and Verification. |
|
+7 days from
Assignment |
| |
5(or 6)/11/2007 |
1st VHDL Programming Exercise
(Combinational Circuits) |
Monday Session
Tuesday Session
|
+7 days from Assignment |
| 5.1 |
5(or 6)/11/2007
In LA 130 |
Software Lab 5.
Binary Memory Devices: Registers and Counters. Design of a
Universal Shift Register, a Ring Counter and a 2-Digit modulo
100 BCD Counter. |
Software/Hardware
Lab 5 (Greek)
(necessary
files) |
|
| 5.2 |
12(or 13)/11/2007
In LA 132 |
Hardware Lab 5.
Implementation of a bi-directional Ring Counter with parallel
load and a modulo 100 BCD Counter with PLDs. Implementation
a Ring Counter with a Universal Shift Register and a modulo
100 BCD counter using discrete components. Testing and Verification. |
|
+7 days from
Assignment |
| |
|
2nd VHDL Programming Exercise
(Sequential Circuits) |
|
|
| 6 |
19(or 20)/11/2007
In LA 130 |
Final Project |
Final Project (Greek)
(necessary
files)
espresso |
|
